Serial interrupt method, device, serial interrupt processing method, and processor

ABSTRACT

A serial interrupt method includes receiving a blank serial interrupt request signal (SerIRQ) and a level signal of a peripheral, based on the blank SerIRQ, generating an indication SerIRQ including an indication interrupt bit (IRQ_n) according to the level signal, and sending the instruction SerIRQ to a processor. The indication IRQ_n identifies the peripheral based on a binary code represented by a first level and a second level.

CROSS-REFERENCES TO RELATED APPLICATION

This application claims priority to Chinese Application No.202110053108.7 filed on Jan. 15, 2021, the entire content of which isincorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally relates to the processor field and,more particularly, to a serial interrupt method, a device, a serialinterrupt processing method, and a processor.

BACKGROUND

A low pin count (LPC) bus is configured to connect a low-bandwidthdevice and an “old” device to a central processing unit (CPU). Thecommon low-bandwidth device includes a basic input-output system (BIOS),a serial interface, a parallel interface, a floppy disk controller, etc.The “old” device includes a programmable interrupt controller, aprogrammable timer, etc. The device connected to the CPU through the LPCbus is collectively referred to as an external device or peripheral. Atpresent, the LPC-based serial interrupt solution includes indicating theperipheral that requests the interrupt to the CPU through the serialinterrupt signal. Thus, the CPU performs a corresponding interruptresponse to the interrupt request of the peripheral.

SUMMARY

Embodiments of the present disclosure provide a serial interrupt method.The method includes receiving a blank serial interrupt request signal(SerIRQ) and a level signal of a peripheral, based on the blank SerIRQ,generating an indication SerIRQ including an indication interrupt bit(IRQ_n) according to the level signal, and sending the indication SerIRQto a processor. The indication IRQ_n identifies the peripheral based ona binary code represented by a first level and a second level.

Embodiments of the present disclosure provide a serial interrupt device,including an interrupt signal receiver, an interrupt request generator,and an interrupt signal transmitter. The interrupt signal receiver isconfigured to receive a blank SerIRQ and a level signal of a peripheral.The interrupt request generator is configured to generate an indicationSerIRQ including an indication IRQ_n according to the level signal basedon the blank SerIRQ. The indication IRQ_n is used to identify theperipheral based on a binary code represented by a first level and asecond level. The interrupt signal transmitter is configured to send theindication SerIRQ to the processor.

Embodiments of the present disclosure provide a serial interruptprocessing method. The method includes receiving an indication SerIRQand performing a serial interrupt response based on the indicationIRQ_n. The indication SerIRQ includes an indication IRQ_n. Theindication IRQ_n is used to identify a peripheral requesting aninterrupt based on a binary code represented by a first level and asecond level.

The serial interrupt method, device, serial interrupt processing method,and processor of embodiments of the present disclosure may use thebinary code represented by the first level and the second level toidentify the peripheral requesting the interrupt to expand the number ofperipherals requesting the interrupts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a system connection based on a low pincount (LPC) bus according to some embodiments of the present disclosure.

FIG. 2A is a schematic diagram of an external electrical level signal inthe electrical level interrupt method according to some embodiments ofthe present disclosure.

FIG. 2B is a schematic diagram of a serial interrupt request signal(SerIRQ) based on LPC according to some embodiments of the presentdisclosure.

FIG. 2C is a schematic diagram of the SerIRQ according to someembodiments of the present disclosure.

FIG. 3 is a schematic flowchart of calculation of a serial interruptmethod according to some embodiments of the present disclosure.

FIG. 4 is a schematic diagram of a SerIRQ according to some embodimentsof the present disclosure.

FIG. 5 is a schematic flowchart of a serial interrupt processing methodaccording to some embodiments of the present disclosure.

FIG. 6 is a schematic block diagram of a serial interrupt deviceaccording to some embodiments of the present disclosure.

FIG. 7 is a schematic block diagram of a processor according to someembodiments of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The technical solutions of embodiments of the present disclosure aredescribed in detail below in connection with the accompanying drawingsof embodiments of the present disclosure. Apparently, describedembodiments are only some embodiments of the present disclosure ratherthan all embodiments. Based on embodiments of the present disclosure,all other embodiments obtained by those of ordinary skill in the artwithout creative efforts shall be within the scope of the presentdisclosure.

The terms “first,” “second,” and similar words used in the presentdisclosure do not indicate any order, quantity, or importance but areonly used to distinguish different components. Similarly, “including,”“containing,” or another similar word means that an element or itemappearing before the word covers the element or item listed after theword and their equivalents but does not exclude other elements or items.Similar words such as “connected” or “coupled” are not limited tophysical or mechanical connections but may include an electricalconnection, no matter a direct or indirect connection.

In a computer system, low-speed peripherals may be connected to acentral processing unit (CPU) through a low pin count (LPC) bus. FIG. 1is a schematic diagram of a system connection based on the LPC busaccording to some embodiments of the present disclosure. Flash memory,an I/O chip (Super I/O), and an embedded controller may be connected tothe LPC bus and connected to a peripheral component interconnect (PCI),e.g., CPU, or a host bus and an industry-standard architecture (ISA) busvia a host. In some embodiments, the peripheral may be connected to theLPC bus through a general-purpose input/output (GPIO) interface.

An LPC-based interrupt type may include a serial interrupt request (IRQ)and a direct memory access (DMA) interrupt. These two interrupt methodsmay share an interrupt number of a general interrupt controller (GIC) ofthe CPU.

In some embodiments, the LPC-based serial IRQ may be different from acommon peripheral level interrupt. In a level interrupt mode, theperipheral may lower a corresponding level signal to realize aninterrupt report. That is, a level signal from the GPIO may only need tohave a descending edge to trigger a complex programmable logic device(CPLD) to cause the CPLD to send an interrupt request to the CPU. Aspecific implementation method may include obtaining a level signalstatus of the GPIO multiple times and storing the level signal status ina register. If two adjacent bits of the register change from 1 to 0, thedescending edge occurs. Similarly, if the two adjacent bits change from0 to 1, an ascending edge occurs. FIG. 2A is a schematic diagram of aperipheral electrical level signal in the level interrupt mode accordingto some embodiments of the present disclosure. FIG. 2A illustrates aclock signal clk_33Mhz and level signals GPIO_1 and GPIO_n. clk_33Mhzrepresents a clock signal with a frequency of 33 MHz. Level signalGPIO_1 corresponds to a peripheral connected to GPIO interface 1 and mayinclude a level signal used to request an interrupt. Level signal GPIO_ncorresponds to a peripheral connected to GPIO interface n and mayinclude a level signal used to request an interrupt. Differentperipherals may correspond to different clock positions of the signal. Atotal number N of peripherals that support the connection may be set bythe CPU. N may be a positive integer. When the peripheral does not needto perform an interrupt request, the level signal may be a high level.When the peripheral needs to perform an interrupt request, theperipheral may lower the level signal at the clock positioncorresponding to the peripheral to realize the interrupt request. Inother words, the peripheral may realize the interrupt request bylowering the signal at the corresponding clock position. The high leveland low level are just examples. When the peripheral does not need toperform an interrupt request, the level signal may be a low level. Whenthe peripheral needs to perform an interrupt request, the peripheral mayincrease the level signal at the clock position corresponding to theperipheral, which is not limited here.

Compared to the level interrupt mode, an LPC-based serial interruptrequest signal (SerIRQ) may include a start frame (start), an interruptbit (IRQ_n), and an end frame (stop). The peripheral may be connected tothe LPC bus through the GPIO interface. When the peripheral needs toperform an interrupt request, the peripheral may lower the signal at thecorresponding clock position and output the signal to a serial interruptdevice. The serial interrupt device may generate the serial interruptrequest signal, including the start frame, the interrupt bit, and theend frame. An identifier of the GPIO interface, which requestsinterrupt, may be marked at the interrupt bit. FIG. 2B is a schematicdiagram of the LPC-based SerIRQ according to some embodiments of thepresent disclosure. GPIO interface n, which requests an interrupt, maygenerate a level signal GPIO_n. The serial interrupt device may generatea SerIRQ based on level signal GPIO_n. The SerIRQ may include the start,the IRQ_n, and the stop. IRO_n located at a low-level position may beused to identify the GPIO interface that requests an interrupt. Forexample, the CPU may recognize the IRQ of the peripheral device based onthe SerIRQ shown in FIG. 2B and perform a corresponding interruptresponse.

In some embodiments, each device frame in the SerIRQ may correspond to 3clock cycles. FIG. 2C is a schematic diagram of the SerIRQ according tosome embodiments of the present disclosure. As shown in FIG. 2C, first,SerIRQ includes the start. The start frame may usually include 4-8 clockcycles, which may be controlled by a host controller or the peripheral.Then, SerIRQ includes IRQ_n. Different peripherals may correspond todifferent clock positions. FIG. 2C shows different device frames,including IRQ0, IRQ1, SMI#, . . . , IRQ14, IRQ15, and IOCHCK. IRQ_n maybe used to identify the peripheral that requests the interrupt throughthe low level of the corresponding position. For example, in FIG. 2C,the position of IRQ1 is the low level, which indicates that theperipheral currently requesting the interrupt corresponds to IRQ1. Eachdevice frame corresponds to 3 clock cycles, which are represented as S,R, and T, respectively. S represents a sample signal (Sample), Rrepresents a reset signal (Recovery), and T represents a turn-aroundsignal (Turn-around). In some embodiments, for IRQ1 requesting theinterrupt, only the S signal is the low level. Generally, the R signaland T signal are high levels. Next, SerIRQ includes the stop. The stopmay usually include 2 or 3 clock cycles.

Table 1 shows the sampling period of the SerIRQ.

TABLE 1 SerIRQ sampling period IRQ/Data Sampling Clock cycles frameframe after start  1 IRQ0  2  2 IRQ1  5  3 SMI#  8  4 IRQ3 11  5 IRQ4 14 6 IRQ5 17  7 IRQ6 20  8 IRQ7 23  9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12IRQ11 35 13 IRQ12 38 14 IRQ13 41 15 IRQ14 44 16 IRQ15 47 17 IOCHCK# 50

As shown in Table 1, for each IRQ/data frame, (IRQ/data frame×3−1) clockcycles are required after the high level of the start. For example, forthe sampling frame IRQ1, 5 clock cycles may be required after the highlevel of the start. That is, for IRQ1, the 5th cycle after the highlevel of the start is the low level, which indicates that IRQ1 requestsan interrupt. For another example, for the sampling frame IRQ5, 6×3−1=17clock cycles are required after the high level of the start. That is,for IRQ5, the 17th cycle after the high level of the start is the lowlevel, which indicates that IRQ5 requests an interrupt. In other words,in the SerIRQ, the low level at the corresponding clock position may beused to identify the peripheral that requests the interrupt. That is,the peripheral identifier and the clock position may have a one-to-onecorrespondence.

Based on FIG. 2C and Table 1, in practical applications, each samplingframe actually needs to include 3 clock cycles, which correspond to theS signal, R signal, and T signal in FIG. 2C, respectively. The S signalmay be used to indicate an interrupt peripheral. To simplify thedescription, only one clock cycle is shown below. That is, only the Ssignal is described.

From the above description, the interrupt peripheral indication methodmay need to consume relatively many clock cycles. When relatively manyperipherals need to be indicated, a large number of clock cycles may berequired, which is not beneficial for fast processing the interruptrequests.

Embodiments of the present disclosure provide a serial interrupt method,which uses binary codes represented by a first level and a second levelto identify the peripheral requesting the interrupt to expand the numberof peripherals requesting the interrupts. Compared with the method ofindicating the interrupt peripheral by the low level of thecorresponding clock position of the SerIRQ shown in FIG. 2B, the numberof peripherals that can be identified may be effectively increased withthe same clock cycles.

FIG. 3 is a schematic diagram of the serial interrupt method accordingto some embodiments of the present disclosure. As shown in FIG. 3 , themethod includes processes S101 to S103. First, at process S101, a blankSerIRQ and a level signal of the peripheral are received. According toembodiments of the present disclosure, the level signal of theperipheral device may be the level signal shown in FIG. 2A and sent bythe peripheral device through the GPIO interface. The level signal ofthe peripheral may correspond to the peripheral.

According to embodiments of the present disclosure, receiving the blankSerIRQ may include receiving the blank SerIRQ from the processor or theperipheral. The blank SerIRQ may include a start, a stop, and a blankIRQ_n located between the start and the stop. The blank IRQ_n mayinclude a first level having a plurality of clock cycles. For example,the blank SerIRQ may refer to the SerIRQ in FIG. 2B, which may notinclude the valid IRQ_n. In other words, the IRQ_n of the blank SerIRQmay be high level (i.e., the first level), which may not includeinformation used to indicate the interrupt peripheral. A serialinterrupt may include a quiet model and a continue model. When the LPCinterrupt is in the quiet model, when there is no interrupt request, theIRQ_n of the SerIRQ line may be high level. When the peripheral needs toreport an interrupt to the CPU, the peripheral may send the start, theIRQ_n, and the stop to the SerIRQ line. Thus, the serial interruptdevice may receive a blank SerIRQ from the peripheral. When the LPCinterrupt is in the continuous model, regardless of whether theperipheral reports an interrupt or not, the CPU will always send out thestart and the stop. When the peripheral needs to report the interrupt,the position of the start may need to be detected, and the peripheralmay lower the clock high level corresponding to the clock positioncorresponding to the peripheral. When the stop is sent, the interruptwill be reported to the GIC of the CPU. In this case, for example, theserial interrupt device may receive the blank SerIRQ from the processor,such as the CPU.

Still referring to FIG. 3 , in process S102, based on the blank SerIRQ,an indication serial interrupt request signal including the indicationIRQ_n is generated according to the level signal. According toembodiments of the present disclosure, the indication IRQ_n may be usedto identify the peripheral requesting the interrupt based on the binarycode represented by the first level and the second level. In processS103, the indication serial interrupt request signal is sent to theprocessor such as the CPU, so that the CPU performs correspondinginterrupt processing.

A process of generating the indication serial interrupt request signal,including the indication IRQ_n according to the level signal (i.e.,process S102) will be described in detail below.

According to some embodiments of the present disclosure, the serialinterrupt method may further include assigning a unique binary code tothe peripheral and storing a correspondence between the level signal ofthe peripheral and the binary code. In the method according to thepresent disclosure, the IRQ_n of the SerIRQ may use the binary code toidentify the peripheral requesting the interrupt, that is, thecorresponding GPIO interface. First, the connected peripheral may becoded. That is, a unique binary code may be assigned to the peripheral.For example, 8 peripherals (denoted as GPIO_0 to GPIO_7) may need to beindicated. GPIO_0 may correspond to binary code 000, GPIO_1 maycorrespond to binary code 001, and so on, GPIO_7 may correspond tobinary code 111.

According to some embodiments of the present disclosure, generating theindication serial interrupt request signal, including the indicationIRQ_n may include determining the binary code of the peripheral based onthe received level signal and the correspondence between the storedlevel signal and the binary code. When the interrupt request isrequired, the peripheral may first send the level signal through theGPIO interface. For example, the peripheral may send the level signalGPOI_1 through the GPOI_1 interface shown in FIG. 2A. Based on the levelsignal GPOI_1 and the correspondence between the level signal and thebinary code, the binary code of the peripheral requesting the interruptmay be determined to be 001. Then, according to the binary code, theblank IRQ_n may be converted into an indication IRQ_n. The first levelof the indication IRQ_n may represent the low binary bit, and the secondlevel of the indication IRQ_n may represent the high binary bit. Forexample, the first level may be the high level, and the second level maybe the low level. That is, the high level of the indication IRQ_n mayrepresent binary 0, and the low level of the indication IRQ_n mayrepresent binary 1.

FIG. 4 is a schematic diagram of the SerIRQ according to someembodiments of the present disclosure. In FIG. 4 , clk_33Mhz is a clocksignal with a frequency of 33 MHz. SerIRQ is an indication SerIRQaccording to embodiments of the present disclosure and includes thestart, the indication IRQ_n, and the stop. FIG. 4 also shows an examplethat 8 peripherals (GPOI_0 to GPIO_7) need to be indicated. That is, nis 3 here. For the indication IRQ_n, assuming that the interfacerequesting the interrupt may be the GPOI_1 interface, the binary codecorresponding to the GPOI_1 interface may be 001. Therefore, in theindication IRQ_n, the binary code 001 may be represented by the highlevel and the low level. When 8 GPIO interfaces need to be indicated,only 3 clock cycles may be required (i.e., 3 S signals shown in FIG. 2C,actually 3×3=9 clock cycles, including 3 S signals, 3 R signals, and 3 Tsignals. FIG. 4 only illustrates the clock cycle of the S signal.). Thestart may take 4-8 clock cycles (FIG. 4 illustrates 4 clock cycles, thatis, 4 clk.). The stop may take 2 or 3 clock cycles. In the quiet model,the stop may take 2 clock cycles. In the continue model, the stop maycorrespond to 3 clock cycles (FIG. 4 illustrates 3 clock cycles, thatis, 3 clk).

In embodiments according to the present disclosure, for N clock cyclesof the indication IRQ_n, the high level or the low level of the signallevel may be taken as 0 or 1 in the binary code. Thus, a total number Nof signal levels may be used to indicate 2^(N) GPIO interfaces.Therefore, the number of clock cycles used to indicate the interruptGPIO interface may be effectively reduced.

According to some embodiments of the present disclosure, the method mayfurther include sending the correspondence between the level signal ofthe peripheral and the binary code to the processor. The processor maybe configured to determine the peripheral indicating the interrupt basedon the correspondence and the indication IRQ_n of the indication SerIRQwhen receiving the indication SerIRQ, that is, determine whichperipheral requests the interrupt. For example, a corresponding storagearea or register may be added to the CPU to store the correspondence.Thus, the CPU may be configured to determine the GPIO interfacerequesting the interrupt based on the correspondence after receiving theSerIRQ. For example, the CPU may know that the GPIO interface requestingthe interrupt of the SerIRQ shown in FIG. 4 is GPIO_1.

According to some embodiments of the present disclosure, a number ofclock cycles included in the blank IRQ_n may be set by the processor.For example, the CPU may set the number of peripherals that can beconnected via the LPC bus, e.g., 16 or 32. After the number ofperipherals is determined, the number of clock cycles included in theblank IRQ_n in the SerIRQ for performing the serial interrupt requestmay be determined. In other words, the number of clock cycles includedin the blank IRQ_n may be determined by the number of connectedperipherals.

According to some embodiments of the present disclosure, the serialinterrupt method may further include setting an interrupt mask register.The interrupt mask register may include a mask indication bit, which isused to indicate whether to mask the serial interrupt. In someembodiments, sending the indication SerIRQ to the processor may includedetecting the mask indication bit in the interrupt mask register andsending the indication SerIRQ to the processor when the mask indicationbit of the interrupt mask register is detected to be a predeterminedbit.

For example, interrupt mask register int_mask[1:0] may be set. Theregister may include, for example, two bits and may be configured todetermine whether to report the received interrupt request to the CPU.As described above, the LPC-based interrupt types may include a serialinterrupt and a DMA interrupt. Therefore, the high bit of the interruptmask register may be used as a serial interrupt mask bit. When the highbit is 1, the serial interrupt may be masked. That is, the SerIRQ maynot be reported to the CPU, and the predetermined bit of the maskindication bit may be 1. When the high bit is 0, the serial interruptmay be reported to the CPU. In addition, the low bit of the interruptmask register may be used as the mask bit for the DMA interrupt, whichfunctions similarly as the mask bit of the serial interrupt. By settingthe interrupt mask bit, whether to report the interrupt may bedetermined by software.

According to another aspect of the present disclosure, embodiments ofthe present disclosure further provide a serial interrupt processingmethod. FIG. 5 is a schematic flowchart of the serial interruptprocessing method according to some embodiments of the presentdisclosure.

As shown in FIG. 5 , the serial interrupt processing method includesprocess S201 and process S202. First, in process S201, the indicationSerIRQ is received. The indication SerIRQ includes an indicationinterrupt bit. The indication interrupt bit may be used to identify theperipheral requesting the interrupt based on the binary code representedby the first level and the second level. Next, in process S202, a serialinterrupt response is performed based on the indication interrupt bit.

According to embodiments of the present disclosure, generating theindication SerIRQ by the serial interrupt device may include receivingthe blank SerIRQ and the level signal of the peripheral and generatingthe indication SerIRQ including the indication IRQ_n according to thelevel signal based on the blank SerIRQ.

According to embodiments of the present disclosure, the blank SerIRQ mayinclude the start, the stop, and the blank IRQ_n located between thestart and the stop. The blank IRQ_n may include the first level of theplurality of clock cycles. The serial interrupt device generating theindication SerIRQ including the indication IRQ_n may include determiningthe binary code of the peripheral based on the received level signal andthe correspondence between the level signal of the peripheral and thebinary code and converting the blank IRQ_n into the indication IRQ_naccording to the binary code. The first level of the indication IRQ_nmay represent the low binary bit. The second level of the indicationIRQ_n may represent the high binary bit.

Therefore, in the serial interrupt processing method according toembodiments of the present disclosure, the indication SerIRQ may begenerated according to the serial interrupt method described above inconnection with FIG. 3 . For a specific generation process, referencemay be made to the above description, which is not repeated here. In theindication IRQ_n of the indication SerIRQ, the high level and the lowlevel of the signal level may be taken as 0 or 1 in the binary code.Thus, the total number N of signal levels may be used to indicate 2^(N)GPIO interfaces. Therefore, the number of clock cycles used by the GPIOinterface to indicate the interrupt may be effectively reduced.

According to embodiments of the present disclosure, the serial interruptprocessing method may further include receiving and storing thecorrespondence between the level signal of the peripheral and the binarycode. In the correspondence, the level signal of the peripheral and thebinary code may have the one-to-one correspondence. Thus, the peripheralrequesting the interrupt may be determined based on the correspondencebetween the level signal of the peripheral and the binary code and theindication IRQ_n. A serial interrupt response may be performed on thedetermined peripheral.

According to another aspect of the present disclosure, embodiments ofthe present disclosure further provide a serial interrupt device 1010.FIG. 6 is a schematic block diagram of the serial interrupt device 1010according to some embodiments of the present disclosure.

As shown in FIG. 6 , the serial interrupt device 1010 includes aninterrupt signal receiver 1011, an interrupt request generator 1012, andan interrupt signal transmitter 1013. According to some embodiments ofthe present disclosure, the interrupt signal receiver 1011 may beconfigured to receive the blank SerIRQ and the level signal of theperipheral. The interrupt request generator 1012 may be configured togenerate the indication SerIRQ including the indication IRQ_n accordingto the level signal based on the blank SerIRQ. The indication interruptbit may be used to identify the peripheral based on the binary coderepresented by the first level and the second level. The interruptsignal transmitter 1013 may be configured to send the indication SerIRQto the processor.

According to some embodiments of the present disclosure, the serialinterrupt device 1010 may further be configured to assign the uniquebinary code to the peripheral and store the correspondence between thelevel signal of the peripheral and the binary code.

According to some embodiments of the present disclosure, the interruptsignal receiver 1011 may be configured to receive the blank SerIRQ fromthe processor or from the peripheral device. The blank SerIRQ mayinclude the start, the stop, and the blank IRQ_n between the start andthe stop. The blank IRQ_n may include the first level of the pluralityof clock cycles.

According to some embodiments of the present disclosure, the interruptrequest generator 1012 may be configured to determine the binary code ofthe peripheral based on the received level signal and the correspondencebetween the stored level signal and the binary code and converting theblank IRQ_n into the indication IRQ_n according to the binary code. Thefirst level of the indication IRQ_n may represent the low binary bit.The second level of the indication IRQ_n may represent the high binarybit.

According to some embodiments of the present disclosure, the interruptsignal transmitter 1013 may further be configured to send thecorrespondence between the level signal of the peripheral and the binarycode to the processor. The processor may be configured to determine theperipheral requesting the interrupt based on the correspondence and theindication IRQ_n of the indication SerIRQ when receiving the indicationserial SerIRQ.

According to some embodiments of the present disclosure, the number ofclock cycles included in the blank IRQ_n may be set by the processor.

According to some embodiments of the present disclosure, the interruptsignal transmitter 1013 may further be configured to set the interruptmask register. The interrupt mask register may include the maskindication bit used to indicate whether to mask the serial interrupt.According to some embodiments of the present disclosure, the interruptsignal transmitter 1013 sending the indication SerIRQ to the processormay include detecting the mask indication bit of the interrupt maskregister and sending the indication SerIRQ to the processor when themask indication bit of the interrupt mask register is detected to be thepredetermined bit.

According to embodiments of the present disclosure, for the processesperformed by the serial interrupt device 1010, reference may be made tothe processes of the serial interrupt method described above inconnection with FIG. 3 , which is not repeated here. For example, theserial interrupt device of embodiments of the present disclosure mayinclude a device located outside of the CPU and configured to report theserial interrupt. The serial interrupt device may be connected to theperipheral through the GPIO interface and may be connected to the CPUthrough the host to realize the interrupt reporting process of theperipheral.

According to another aspect of the present disclosure, embodiments ofthe present disclosure further provide a processor 1020. FIG. 7 is aschematic block diagram of the processor 1020 according to someembodiments of the present disclosure.

As shown in FIG. 7 , the processor 1020 includes a signal receiver 1021and an interrupt responder 1022. According to some embodiments of thepresent disclosure, the signal receiver 1021 may be configured toreceive the indication SerIRQ. The indication SerIRQ may include theindication interrupt bit. The indication interrupt bit may be used toidentify the peripheral requesting the interrupt based on the binarycode represented by the first level and the second level. The interruptresponder 1022 may be configured to perform serial interrupt responsebased on the indication interrupt bit.

According to some embodiments of the present disclosure, the signalreceiver 1021 may further be configured to receive and store thecorrespondence between the level signal of the peripheral and the binarycode. In the correspondence, the level signal of the peripheral and thebinary code may have the one-to-one correspondence.

According to some embodiments of the present disclosure, generating theindication SerIRQ by the serial interrupt device may include receivingthe blank SerIRQ and the level signal of the peripheral and generatingthe indication SerIRQ including the indication IRQ_n according to thelevel signal based on the blank SerIRQ. The serial interrupt device maybe, for example, the serial interrupt device as shown in FIG. 6 and maybe configured to implement the serial interrupt method shown in FIG. 3 .

According to some embodiments of the present disclosure, the blankSerIRQ may include the start, the stop, and the blank IRQ_n locatedbetween the start and the stop. The blank IRQ_n may include the firstlevel of the plurality of clock cycles. The serial interrupt devicegenerating the indication SerIRQ including the indication IRQ_n mayinclude determining the binary code of the peripheral based on thereceived level signal and the correspondence between the level signal ofthe peripheral and the binary code and converting the blank IRQ_n intothe indication IRQ_n according to the binary code. The first level ofthe indication IRQ_n may represent the low binary bit, and the secondlevel of the indication IRQ_n may represent the high binary bit.

According to some embodiments of the present disclosure, the interruptresponder 1022 may be configured to determine the peripheral requestingthe interrupt based on the correspondence between the level signal ofthe peripheral and the binary code and the indication IRQ_n andperforming the serial interrupt response to the peripheral.

With the serial interrupt method, device, serial interrupt processingmethod, and processor of embodiments of the present disclosure, thebinary code represented by the first level and the second level may beused to identify the peripheral that requests the interrupt. Thus, thenumber of peripherals requesting the interrupts may be expanded.

Those skilled in the art can understand that various modifications andimprovements may be made to the content disclosed in the presentdisclosure. For example, the devices or components described above maybe implemented by hardware, software, firmware, or a combinationthereof.

In addition, although the present disclosure makes various references toa certain unit in the system according to embodiments of the presentdisclosure, any number of different units may be used and run on theclient end and/or the server. The unit is merely illustrative. Differentunits may be used for different aspects of the system and method.

In the present disclosure, flowcharts are used to illustrate theprocesses of the method according to embodiments of the presentdisclosure. Processes in the front or back are not necessarily performedin a precise order. The processes may be performed in reverse order orsimultaneously. Meanwhile, another operation may also be added to theprocesses.

Those of ordinary skill in the art can understand that all or a part ofthe processes of the above method may be completed by a computer programinstructing related hardware. The program may be stored in acomputer-readable storage medium, such as a read-only memory, a magneticdisk, or an optical disk. In some embodiments, all or a part of theprocesses of embodiments of the present disclosure may also beimplemented using one or more integrated circuits. Correspondingly,modules/units of embodiments of the present disclosure may beimplemented in the form of hardware or software functional modules. Thepresent disclosure is not limited to the combination of any specificform of hardware and software.

Unless otherwise defined, all the terms used here may have the samemeaning as commonly understood by those of ordinary skill in the art.Terms such as those defined in an ordinary dictionary should beinterpreted as having meanings consistent with their meanings in thecontext of the related technology, and should not be interpreted inidealized or extremely formalized meanings unless specified here.

The above may be an explanation of the present disclosure and should notbe considered as a limitation to the present disclosure. Althoughseveral exemplary embodiments of the present disclosure have beendescribed, those skilled in the art may easily understand that manymodifications may be made to exemplary embodiments without departingfrom the novel teaching and advantages of the present disclosure.Therefore, all these modifications are intended to be included in thescope of the invention defined by the claims. The above may be anexplanation of the present disclosure and should not be considered aslimited to specific embodiments disclosed. Modifications to disclosedembodiments and other embodiments are intended to be included in thescope of the claims. The present invention is defined by the claims andtheir equivalents.

What is claimed is:
 1. A serial interrupt method comprising: receiving ablank serial interrupt request signal (SerIRQ) from either a processoror a peripheral and a peripheral level signal from the peripheral; basedon the blank SerIRQ, generating an indication SerIRQ including aplurality of indication interrupt bits according to the peripheral levelsignal, the plurality of indication interrupt bits including a binarycode represented by a first level and a second level to identify theperipheral; and sending the indication SerIRQ to the processor.
 2. Themethod of claim 1, further comprising: assigning the binary code to theperipheral before uniquely identifying the peripheral; and storing acorrespondence between the peripheral level signal of the peripheral andthe binary code in advance.
 3. The method of claim 2, wherein: the blankSerIRQ includes a start, a stop, and a plurality of blank interrupt bitslocated between the start and the stop, and the plurality of blankinterrupt bits are represented in the form of the first level having aplurality of clock cycles.
 4. The method of claim 3, wherein generatingthe indication SerIRQ including the plurality of indication interruptbits includes: determining the binary code of the peripheral based onthe received peripheral level signal and the stored correspondencebetween the peripheral level signal and the binary code; and convertingthe plurality of blank interrupt bits into the plurality of indicationinterrupt bits according to the binary code, the first levelrepresenting a low binary bit, and the second level representing a highbinary bit.
 5. The method of claim 2, further comprising: sending thecorrespondence between the peripheral level signal of the peripheral andthe binary code to the processor, wherein in response to receiving theindication SerIRQ, based on the correspondence and the plurality ofindication interrupt bits of the indication SerIRQ, the processor isconfigured to determine the peripheral requesting an interrupt.
 6. Themethod of claim 3, wherein a number of the clock cycles included in theplurality of blank interrupt bits is set by the processor.
 7. The methodof claim 1, further comprising: setting an interrupt mask register inadvance, the interrupt mask register including a mask indication bitused to indicate whether to mask a serial interrupt.
 8. The method ofclaim 7, wherein sending the indication SerIRQ to the processorincludes: detecting the mask indication bit of the interrupt maskregister; and in response to detecting that the mask indication bit ofthe interrupt mask register is a predetermined bit, sending theindication SerIRQ to the processor.
 9. A serial interrupt devicecomprising: an interrupt signal receiver configured to receive a blankserial interrupt request signal SerIRQ) from either a processor or aperipheral and a peripheral level signal from the peripheral; aninterrupt request generator configured to generate an indication SerIRQincluding a plurality of indication interrupt bits according to theperipheral level signal based on the blank SerIRQ, the plurality ofindication interrupt bits including a binary code represented by a firstlevel and a second level to identify the peripheral; and an interruptsignal transmitter configured to send the indication SerIRQ to theprocessor.
 10. The serial interrupt device of claim 9, wherein theserial interrupt device is further configured to: assign the binary codeto the peripheral before uniquely identifying the peripheral; and storea correspondence between the peripheral level signal of the peripheraland the binary code in advance.
 11. The serial interrupt device of claim10, wherein: the blank SerIRQ includes a start, a stop, and a pluralityof blank interrupt bits located between the start and the stop, and theplurality of blank interrupt bits are represented in the form of thefirst level having a plurality of clock cycles.
 12. The serial interruptdevice of claim 11, wherein the interrupt request generator is furtherconfigured to: determine the binary code of the peripheral based on thereceived peripheral level signal and the stored correspondence betweenthe peripheral level signal and the binary code; and convert theplurality of blank interrupt bits into the plurality of indicationinterrupt bits according to the binary code, the first levelrepresenting a low binary bit, and the second level representing a highbinary bit.
 13. The serial interrupt device of claim 10, wherein theinterrupt signal transmitter is further configured to: send thecorrespondence between the peripheral level signal of the peripheral andthe binary code to the processor, in response to receiving theindication SerIRQ, based on the correspondence and the plurality ofindication interrupt bits of the indication SerIRQ, the processor beingconfigured to determine the peripheral requesting an interrupt.
 14. Theserial interrupt device of claim 11, wherein a number of the clockcycles included in the plurality of blank interrupt bits is set by theprocessor.
 15. The serial interrupt device of claim 9, wherein theinterrupt signal transmitter is further configured to: set in advance aninterrupt mask register including a mask indication bit used to indicatewhether to mask a serial interrupt.
 16. A serial interrupt processingmethod comprising: receiving, by a processor, an indication SerIRQ froma serial interrupt device, the indication SerIRQ including a pluralityof indication interrupt bits, and the plurality of indication interruptbits including a binary code represented by a first level and a secondlevel to identify a peripheral requesting an interrupt; and performing,by the processor, a serial interrupt response based on the plurality ofindication interrupt bits.
 17. The method of claim 16, wherein: acorrespondence between a peripheral level signal of the peripheral andthe binary code is received and stored by the serial interrupt device,the peripheral level signal of the peripheral and the binary code havinga one-to-one correspondence.
 18. The method of claim 17, wherein theindication SerIRQ is generated by the serial interrupt device by:receiving a blank SerIRQ from either the processor or the peripheral andthe peripheral level signal from the peripheral; and based on the blankSerIRQ, generating the indication SerIRQ including the plurality ofindication interrupt bits according to the peripheral level signal. 19.The method of claim 18, wherein: the blank SerIRQ includes a start, astop, and a plurality of blank interrupt bits located between the startand the stop, the plurality of blank interrupt bits are represented inthe form of the first level having a plurality of clock cycles; and theserial interrupt device generating the indication SerIRQ including theplurality of indication interrupt bits includes: determining the binarycode of the peripheral based on the received peripheral level signal andthe correspondence between the peripheral level signal of the peripheraland the binary code; and according to the binary code, converting theplurality of blank interrupt bits into the plurality of indicationinterrupt bits, the first level representing a low binary bit, and thesecond level representing a high binary bit.
 20. The method of claim 19,wherein performing the serial interrupt response based on the pluralityof indication interrupt bits includes: determining the peripheralrequesting the interrupt based on the plurality of indication interruptbits; and performing the serial interrupt response to the interruptrequested by the peripheral.